1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a flash EPROM array that incorporates segment select lines to provide enhanced read access speed and true segment erase.
2. Discussion of the Prior Art
In a "flash" EPROM device, all cells in the data storage array are electrically erased in a single operation. That is, unlike electrically erasable programmable read only memories (EEPROMs), which require larger storage cell size, individual storage cells in a flash EPROM array cannot be selectively erased.
Albert Bergemont's U.S. patent application Ser. No. 07/830,938, referenced above, discloses a novel "contactless" flash EPROM array architecture that provides reduced cell size and ease of scalability while retaining the programming and erase simplicity of conventional flash EPROMs.
The Bergemont contactless EPROM array utilizes cross-point cells formed in a P-type silicon substrate. The array comprises a layer of gate oxide formed on a P-type silicon substrate. Parallel strips of oxide/nitride/oxide (ONO) and underlying first polysilicon (Poly1) are formed on the gate oxide, the Poly1 providing the floating gates for the cells of the array. Buried N+ bit lines are formed in the substrate between the ONO/Poly1 strips. Alternate buried N+ bit lines have additional N-type dopant introduced thereto to form graded source lines that alternate with buried N+ drain lines. The graded source bit lines are contacted by metal in segmented fashion, i.e. there is only one source contact for every 32 or 64 cells in a given column of the array. The intermediate buried N+ drain lines are uncontacted. The array's Poly2 word lines are formed perpendicular to the ONO/Poly1 strips such that the word lines are separated from the Poly1 floating gates by the ONO to define "cross-point" cells. Each buried N+ drain line is electrically connectable to one of its adjacent graded source lines via a first select transistor that has its gate provided by a first Poly2 select line and to the other adjacent graded source line via a second select transistor that has its gate provided by a second select line. The first and second select transistors are also cross-point flash EPROM cells defined by the intersection of Poly2 select lines and the N+ bit lines.
As explained by Boaz Eitan in U.S. patent application Ser. No. 539,657, filed Jun. 13, 1990, now U.S. Pat. No. 5,204,835, the use of segmented bit lines and select transistors inhibits drain turn-on in unselected cells in unselected segments during programming.
A selected cell in the Bergemont array is programmed by maintaining the word line of the selected cell at the programming voltage. The first adjacent graded source line is maintained at a high voltage, while the second adjacent graded source line is maintained at a low voltage. A high voltage level is then applied to the first select line while the second select line is held at the low voltage level to pull up the high voltage on the intermediate noncontacted drain bit line. Thus, hot electrons are injected onto the floating gate of the selected cell.
The Bergemont array is erased by applying an erase voltage to each of the graded source lines and holding both the first select line and the second select line at the low voltage level. Thus, for each programmed flash EPROM cell in the array, electrons tunnel from the floating gate of the cell to the graded source of the cell.
While the above-described Bergemont flash EPROM array provides significant advantages over the prior art, it, like other prior art flash EPROM arrays, is limited to full array erase. Also, since all segments of the array must be precharged for a read operation, read access speed to a selected EPROM cell is limited.
Therefore, it would be desireable to have available a flash EPROM array that provides increased read access speed and true segment erase.